AI Chip Ecosystem

From Dispatcher to Core Compute: How AI Is Reshaping the Chip Ecosystem

In traditional computing architectures, the CPU has long been the undisputed commander—orchestrating all tasks and managing data flows. But in the era of large AI models, this hierarchy is being upended. Jensen Huang's "AI factory" concept positions GPU/NPU as the new compute center, with the CPU relegated to a co-processor role. This shift carries profound implications across the semiconductor supply chain.

The Triple Jump of AI Compute Demands

AI's chip appetite is expanding from cloud to edge across three tiers:

Cloud training: trillion-parameter foundation models demand tens of thousands of accelerators. NVIDIA H200/B200 remain supply-constrained, fueling chasers like AMD MI300X and Intel Gaudi 3—though CUDA's ecosystem moat remains formidable
Cloud inference: GPT-5-class inference requires dozens of TFLOPS per query. Purpose-built inference chips (Groq LPU, Cerebras CS-3) pitch ultra-low latency as their differentiator, attempting to siphon market share
Edge inference: running 7B-13B models locally on phones, PCs, and vehicles is becoming table stakes. Qualcomm Snapdragon 8 Elite (45 TOPS NPU), Apple M4 (38 TOPS Neural Engine), and Intel Lunar Lake (48 TOPS NPU) bake AI acceleration into the SoC baseline

This triple-tier expansion not only drives demand for advanced nodes (3nm/2nm) but also ignites adjacent ecosystems: DDR5/HBM, CXL interconnects, and advanced packaging (CoWoS).

Three Breakout Paths for Chinese Chips

Under tightening US export controls, Chinese chip vendors are pursuing three distinct paths:

GPU general-purpose path: Biren Technology and Moore Threads take aim at NVIDIA's training market—but face material gaps in process technology and ecosystem maturity
NPU application-specific path: Horizon Robotics and Black Sesame focus on autonomous driving; Cambricon and Denglin target cloud inference, trading generality for energy-efficiency advantage
MCU+NPU fusion path: Nuvoton M55M1 and Nations Technologies N32H series integrate lightweight NPUs onto conventional MCUs, targeting long-tail edge AI scenarios—home appliances, sensor nodes, industrial predictive maintenance

The third path holds the most practical relevance for HSY customers: MCU+NPU fusion requires no advanced process nodes (28nm-40nm suffices), keeps power consumption in check, and avoids forcing customers to build AI software stacks from scratch.

Heterogeneous Computing: Coexistence, Not Replacement

Despite the GPU/NPU spotlight, heterogeneous computing is the real endgame. An AI server needs CPUs for system management, GPUs for matrix operations, DPUs for network offload, and FPGAs for flexible acceleration. These chips are not in a zero-sum game—they find their optimal roles through layered collaboration.

CPU: system scheduling, control flows, lightweight inference
GPU/NPU: matrix multiplication, massively parallel computation
FPGA: low-latency real-time inference, protocol conversion, cryptographic acceleration
DPU/SmartNIC: data movement, network protocol offload

HSY Perspective

The explosive growth of AI compute demand presents dual opportunities for HSY customers. Downstream AI hardware makers (servers, switches, edge AI devices) are driving sustained demand for MCUs, power management ICs, and communication modules. Meanwhile, MCU+NPU fusion solutions allow traditional embedded customers to enter the AI space at minimal cost. HSY recommends industrial control, home appliance, and automotive electronics customers monitor the Nuvoton M55M1 and Nations Technologies N32H series, leveraging their existing MCU development experience to transition smoothly into edge AI applications.

Source: Sina Finance industry analysis, June 3, 2026